1. Field of the Invention
The present invention relates in general to a semiconductor device and a method of manufacturing the same, and in particular to a semiconductor device formed on an insulating layer and a method of manufacturing the same.
2. Description of the Background Art
In order to improve the performance of semiconductor devices, there have been developed semiconductor devices in which circuit elements are isolated by dielectrics and a floating capacitance is small. For forming transistors on a thin silicon film on an insulating film, which will be referred to as an SOI (Silicon On Insulation) layer, an MESA isolating method is used for isolating the transistors from each other. According to this MESA isolating method, the isolated transistors are formed at completely isolated or insular SOI layers, respectively. This brings about many advantages such as prevention of influence of latch-up between adjacent transistors.
FIGS. 198 to 206 are cross sections showing a process of manufacturing an SOI-MOSFET using a conventional MESA isolating method. Referring to FIG. 206, description will be given on a structure of the SOI-MOSFET formed by the conventional MESA solating method. In this SOI-MOSFET, a buried oxide film 2 is formed on a silicon substrate 1. SOI layers 3 are formed at predetermined regions on buried oxide film 2 with a predetermined space between each other. Silicon substrate 1, buried oxide film 2 and SOI layers 3 form an SOI substrate. Source/drain regions 3e and 3f having an LDD structure are formed on SOI layer 3 at an PMOS region with a predetermined space between each other and are located at opposite sides of a channel region 3g. Titanium silicide films 8a are formed on the surfaces of source/drain regions 3e and 3f. A gate electrode 6 is formed on channel region 3g with a gate oxide film 5 therebetween. Titanium silicide film 8a is also formed also on the upper surface of gate electrode 6. Side wall oxide films 13 are formed in contact with side surfaces of gate electrode 6.
On SOI layer 3 at an NMOS region, there are formed source/drain regions 3b and 3c having an LDD structure with a predetermined space between each other and are located at opposite sides of a channel region 3d. A gate electrode 6 is formed on channel region 3d with a gate oxide film 50 therebetween. Side wall oxide films 13 are formed in contact with side surfaces of gate electrode 6. Titanium silicide films 8a are formed on source/drain regions 3b and 3c and gate electrode 6. The PMOS and NMOS regions are covered with an interlayer oxide film 9. Contact holes are formed at regions of interlayer oxide film 9 located above source/drain regions 3b, 3c, 3e and 3f. There are provided metal interconnection layers 10 having portions filling the contact holes. Gate electrodes 6 are formed of polycrystalline silicon films containing phosphorus (P) at 1×1020/cm2 or more. Titanium silicide films 8a are formed for reducing resistances of source/drain regions 3b, 3c, 3e and 3f and gate electrode 6.
Referring to FIGS. 198 to 206, a process of manufacturing the SOI-MOSFET using the conventional MESA isolating method will be described below.
As shown in FIG. 198, buried oxide film 2 is first formed on silicon substrate 1. After forming SOI layer 3 on buried oxide film 2, a surface of SOI layer 3 is oxidized to form oxide film 5 having a thickness from about 100 Å to about 200 Å. A resist 201 is formed at predetermined regions on oxide film 5. Using resist 201 as a mask, dry etching is effected on oxide film 5 and SOI layer 3. Thereby, SOI layers 3 forming active regions of transistors spaced by a predetermined distance are formed as shown in FIG. 199.
In this isolating method, predetermined regions of SOI layer 3 are removed by the etching to break electrical connection between adjacent transistors, which is called the MESA isolating method. Thereafter, resist 201 is removed. A resist 202 is formed to cover the PMOS region. Using resist 202 as a mask, boron ions are implanted into SOI layer 3 at the NMOS region under the conditions of 20 keV and 1×1012–3×1012/cm2. This implantation is performed for forming the channel region of NMOSFET. Thereafter, resist 202 is removed.
As shown in FIG. 200, a resist 203 is then formed over the NMOS region. Using resist 203 as a mask, phosphorus ions are implanted into SOI layer 3 at the PMOS region under the conditions of 30 kev and 1×1011–3×1011/cm2. This implantation is performed for forming the channel region of the PMOSFET. Thereafter, resist 203 is removed. Oxide film 5 on SOI layer 3 is removed.
As shown in FIG. 201, gate oxide film 50 having a thickness of about 100 Å is formed over each SOI layer 3. Polycrystalline silicon layer 6 containing phosphorus at 1×1020/cm2 or more and having a thickness of about 2000 Å is formed over gate oxide films 50 and buried oxide film 2. A resist 204 is formed at predetermined regions on polycrystalline silicon layer 6. Using resist 204 as a mask, dry etching is effected on polycrystalline silicon layer 6 to form gate electrodes 6 as shown in FIG. 202. After removing resist 204 (shown in FIG. 201), a resist 205 is formed over the PMOS region. Using resist 205 and gate electrodes 6 at the NMOS region as a mask, phosphorus ions are implanted into SOI layer 3 at the NMOS region under the conditions of 40 keV and 1×1013–3×1013/cm2. This implantation is performed for forming a lightly doped region in the LDD structure. Thereafter, resist 205 is removed.
As shown in FIG. 203, a resist 206 is formed over the NMOS region. Using resist 206 as a mask, boron ions are implanted into SOI layer 3 at the PMOS region under the conditions of 20 keV and 1×1013–3×1013/cm2. This implantation is performed for forming a lightly doped region forming the LDD structure of the PMOSFET. Thereafter, resist 206 is removed.
As shown in FIG. 204, side wall insulating films 13 are formed in contact with side surfaces of gate electrode 6. Side wall insulating films 13 may be formed by effecting anisotropic etching on an insulating film (now shown) which was formed over gate electrode 6. Thereafter, a resist 207 is formed over the PMOS region. Using resist 207, gate electrode 6 at the NMOS region and side wall insulating films 13 as a mask, phosphorus ions are implanted into SOI layer 3 at the NMOS region under the conditions of 40 keV and 4×1015–6×1015/cm2. This implantation is performed for forming heavily doped regions forming the source/drain regions in the NMOSFET. Thereafter, resist 207 is removed. Arsenic may be used as implanted ion species for the source/drain regions.
As shown in FIG. 205, a resist 208 is formed over the NMOS region. Using resist 208, gate electrode 6 at the PMOS region and side wall insulating films 13 as a mask, boron ions are implanted into SOI layer 3 at the PMOS region under the conditions of 20 keV and 4×1015–6×1015/cm2. This implantation is performed for forming heavily doped regions forming the source/drain regions in the PMOSFET. Thereby, source/drain regions 3e and 3f having the LDD structure are formed. Thereafter, resist 208 is removed.
Then, as shown in FIG. 206, titanium silicide layers 8a are formed on the surfaces of source/drain regions 3b, 3c, 3e and 3f and gate electrodes 6. After forming interlayer insulating film 9 of about 7000 Å in thickness over the whole surface, the contact holes are formed at regions located above source/drain regions 3b, 3c, 3e and 3f. The aluminum layer having portions filling the contact holes is formed and then is patterned to form metal interconnection layers 10. In this manner, the SOI-CMOSFETs isolated by the conventional MESA isolating method are completed as shown in FIG. 206.
However, in the conventional semiconductor device thus constructed, a parasitic transistor is formed at a region where gate electrode 6 and SOI layer 3 overlap with each other, and in particular at a region near the side surface of SOI layer 3. FIG. 207 is a cross section taken along line perpendicular to the section shown in FIG. 206. Referring to FIG. 207, an electric field concentrates at an upper end of SOI layer 3 where the parasitic transistor is formed, and an interface level is formed at the upper end due to the process. Therefore, a disadvantage occurs in connection with subthreshold characteristics of a regular MOS transistor formed at SOI layer 3. More specifically, since the threshold voltage of parasitic transistor lowers as already described, such a disadvantage is caused that the parasitic transistor is turned on by a voltage lower than the threshold voltage of the regular transistor. This and other disadvantages are specifically disclosed in “ELECTRONICS LETTERS 18th, August”, Vol. 19, No. 17, 1983, pp. 684–685.
In order to overcome the above-noted problem, there have been proposed manufacturing processes for preventing concentration of electric field at the upper end of SOI layer 3. These are disclosed, for example, in U.S. Pat. No. 4,753,896. FIGS. 208 to 214 are cross sections showing the proposed manufacturing process. Referring to FIGS. 208 to 214, the proposed manufacturing process will be described below.
As shown in FIG. 208, buried insulating film 2 is first formed on semiconductor substrate 1. SOI layer 3 is formed on buried insulating film 2. A nitride film 4a is formed at a predetermined region of SOI layer 3 with oxide film 5 therebetween. Using nitride film 4a as a mask, impurity is ion-implanted into SOI layer 3. This ion implantation is performed for raising a threshold voltage of a parasitic transistor.
As shown in FIG. 209, side wall nitride film 4b is then formed in contact with side surfaces of nitride film 4a and oxide film 5. Using side wall nitride film 4b and nitride film 4a as a mask, dry etching is effected on SOI layer 3 to form patterned SOI layer 3 shown in FIG. 210.
As shown in FIG. 211, an oxide film 120 is formed to cover nitride film 4a, side wall nitride film 4b, SOI layer 3 and buried oxide film 2. Anisotropic etching is effected on oxide film 120 to form side wall oxide films 120 as shown in FIG. 213. Thereafter, nitride film 4a, side wall nitride film 4b and oxide film 5 are removed. As shown in FIG. 214, gate oxide film 50 is formed over SOI layer 3 and side wall oxide film 120, and then gate electrode 6 is formed on gate oxide film 50. In the structure thus formed, since side wall oxide film 120 is interposed between the side surface of SOI layer 3 and gate electrode 6, a portion of the parasitic transistor corresponding to a gate oxide film has a large thickness, so that an electric field applied from gate electrode 6 in the parasitic transistor is weaken. Consequently, the subthreshold characteristics of regular transistor is prevented from being affected by the characteristics of the parasitic transistor.
However, the proposed manufacturing process may suffer from the following problem. FIGS. 215 to 217 are cross sections showing the problem of the proposed manufacturing process. In the proposed manufacturing process, heat treatment is performed to activate the impurity implanted into SOI layer 3 after forming oxide film 120 at the step shown in FIG. 212. During this heat treatment, oxidant moves up to the bottom and upper surfaces of the side portion of SOI layer 3 as shown in FIG. 215. Thereby, the side portion of SOI layer 3 is shaped into an acute form. In this state, the side wall oxide film 120 is formed as shown in FIG. 216, and then gate oxide film 50 and gate electrode 6 are formed. In this case, an electric field concentrates at the side portion of SOI layer 3. As a result, the threshold voltage of parasitic transistor lowers, and thus the parasitic transistor tends to be turned on. Thereby, the subthreshold characteristics of regular transistor are adversely affected.
In the process of forming side wall oxide film 120 shown in FIGS. 212 and 213, it is necessary to perform over-etching on oxide film 120 for completely removing oxide film 120 on nitride film 4a when performing the anisotropic etching on oxide film 120. As a result of this over-etching, side wall oxide film 120 is formed not to cover the upper portion of side surface of SOI layer 3 as shown in FIG. 219. Gate oxide film 50 and gate electrode 6 are formed over this structure as shown in FIG. 219, whereby the electric field disadvantageously concentrates at the upper side end of SOI layer 3. This lowers the threshold voltage of parasitic transistor, and thus the subthreshold characteristics of regular transistor are adversely affected. As described above, various problems arise in the manufacturing process proposed in the prior art, and consequently, it is difficult to improve the subthreshold characteristics of regular transistor.